diff --git a/core/lib.rs b/core/lib.rs
index cfd94dd51..d9be4e0f6 100644
--- a/core/lib.rs
+++ b/core/lib.rs
@@ -162,7 +162,7 @@ impl Database {
                 .try_write()
                 .expect("lock on schema should succeed first try");
             let syms = conn.syms.borrow();
-            parse_schema_rows(rows, &mut schema, io, syms.deref())?;
+            parse_schema_rows(rows, &mut schema, io, syms.deref(), None)?;
         }
         Ok(db)
     }
@@ -527,6 +527,10 @@ impl Statement {
         }
     }
 
+    pub fn set_mv_tx_id(&mut self, mv_tx_id: Option<u64>) {
+        self.state.mv_tx_id = mv_tx_id;
+    }
+
     pub fn interrupt(&mut self) {
         self.state.interrupt();
     }
diff --git a/core/util.rs b/core/util.rs
index b16c29de3..3e141f9a9 100644
--- a/core/util.rs
+++ b/core/util.rs
@@ -41,8 +41,10 @@ pub fn parse_schema_rows(
     schema: &mut Schema,
     io: Arc<dyn IO>,
     syms: &SymbolTable,
+    mv_tx_id: Option<u64>,
 ) -> Result<()> {
     if let Some(mut rows) = rows {
+        rows.set_mv_tx_id(mv_tx_id);
         let mut automatic_indexes = Vec::new();
         loop {
             match rows.step()? {
diff --git a/core/vdbe/mod.rs b/core/vdbe/mod.rs
index cb88cc06b..3dd208db1 100644
--- a/core/vdbe/mod.rs
+++ b/core/vdbe/mod.rs
@@ -235,7 +235,7 @@ pub struct ProgramState {
     deferred_seek: Option<(CursorID, CursorID)>,
     ended_coroutine: Bitfield<4>, // flag to indicate that a coroutine has ended (key is the yield register. currently we assume that the yield register is always between 0-255, YOLO)
     regex_cache: RegexCache,
-    mv_tx_id: Option<crate::mvcc::database::TxID>,
+    pub(crate) mv_tx_id: Option<crate::mvcc::database::TxID>,
     interrupted: bool,
     parameters: HashMap<NonZero<usize>, OwnedValue>,
     halt_state: Option<HaltState>,
@@ -3034,6 +3034,7 @@ impl Program {
                         &mut schema,
                         conn.pager.io.clone(),
                         &conn.syms.borrow(),
+                        state.mv_tx_id,
                     )?;
                     state.pc += 1;
                 }