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Merge pull request #4492 from zvonkok/pcie-topology
runtime: fix PCIe topology for GPUDirect use-case
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@@ -140,6 +140,9 @@ type qemuArch interface {
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// appendPCIeRootPortDevice appends a pcie-root-port device to pcie.0 bus
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appendPCIeRootPortDevice(devices []govmmQemu.Device, number uint32, memSize32bit uint64, memSize64bit uint64) []govmmQemu.Device
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// appendPCIeSwitch appends a ioh3420 device to a pcie-root-port
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appendPCIeSwitchPortDevice(devices []govmmQemu.Device, number uint32, memSize32bit uint64, memSize64bit uint64) []govmmQemu.Device
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// append vIOMMU device
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appendIOMMU(devices []govmmQemu.Device) ([]govmmQemu.Device, error)
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@@ -183,7 +186,8 @@ const (
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defaultBridgeBus = "pcie.0"
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defaultPCBridgeBus = "pci.0"
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maxDevIDSize = 31
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pcieRootPortPrefix = "rp"
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maxPCIeRootPort = 16 // Limitation from QEMU
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maxPCIeSwitchPort = 16 // Limitation from QEMU
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)
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// This is the PCI start address assigned to the first bridge that
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@@ -677,17 +681,17 @@ func (q *qemuArchBase) appendVhostUserDevice(ctx context.Context, devices []govm
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}
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func (q *qemuArchBase) appendVFIODevice(devices []govmmQemu.Device, vfioDev config.VFIODev) []govmmQemu.Device {
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pciDevice := vfioDev.(config.VFIOPCIDev)
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if pciDevice.BDF == "" {
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if vfioDev.BDF == "" {
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return devices
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}
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devices = append(devices,
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govmmQemu.VFIODevice{
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BDF: pciDevice.BDF,
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VendorID: pciDevice.VendorID,
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DeviceID: pciDevice.DeviceID,
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Bus: pciDevice.Bus,
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BDF: vfioDev.BDF,
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VendorID: vfioDev.VendorID,
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DeviceID: vfioDev.DeviceID,
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Bus: vfioDev.Bus,
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},
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)
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@@ -803,6 +807,13 @@ func (q *qemuArchBase) appendPCIeRootPortDevice(devices []govmmQemu.Device, numb
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return genericAppendPCIeRootPort(devices, number, q.qemuMachine.Type, memSize32bit, memSize64bit)
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}
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// appendPCIeSwitchPortDevice appends a PCIe Switch with <number> ports
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func (q *qemuArchBase) appendPCIeSwitchPortDevice(devices []govmmQemu.Device, number uint32, memSize32bit uint64, memSize64bit uint64) []govmmQemu.Device {
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return genericAppendPCIeSwitchPort(devices, number, q.qemuMachine.Type, memSize32bit, memSize64bit)
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}
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// getBARsMaxAddressableMemory we need to know the BAR sizes to configure the
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// PCIe Root Port or PCIe Downstream Port attaching a device with huge BARs.
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func (q *qemuArchBase) getBARsMaxAddressableMemory() (uint64, uint64) {
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pci := nvpci.New()
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